FPGA Notch the third and PCIe Block Diagram
Today I implemented the Fixed Point Version of my Filter in my IP Core. For the Floating Point Version I were just able to use generate and could implement n Independent Filter for every channel. Cause the Fixed Point Filter is much faster I can Pipeline it through all channels and it's still fast enough. That gives me this total resource consumption of my IP: Slice LUT's -> 2745 (4.33%) Slice Registers -> 5392 (4.25%) F7 Muxes -> 408 (1.29%) RAMB18 -> 0 DSPs -> 16 (6.67%) The Time needed for Filtering 8 Channels is 9.56µs. So with this resource usage I think there is still enough Space to implement a STFT on the Artix 7 ;-) But I won't talk too much about the Filter Implementation. I think it could be interesting to Show you the PCIe Block Diagram and what's important to get it ready. MSI Request -> '0' axi_aresetn -> '1' Utility Buffer: Set to IBUFDSGTE AXI Memory Mapped to PCI Ex...