FPGA Notch the third and PCIe Block Diagram
Today I implemented the Fixed Point Version of my Filter in my IP Core.
For the Floating Point Version I were just able to use generate and could implement n Independent Filter for every channel.
Cause the Fixed Point Filter is much faster I can Pipeline it through all channels and it's still fast enough.
That gives me this total resource consumption of my IP:
So with this resource usage I think there is still enough Space to implement a STFT on the Artix 7 ;-)
But I won't talk too much about the Filter Implementation.
I think it could be interesting to Show you the PCIe Block Diagram and what's important to get it ready.
MSI Request -> '0'
axi_aresetn -> '1'
Utility Buffer:
When you go to the Address Editor you have to map the AXI Slave to the Address Map.
Then you see there the Address Range, the Start Address of your Slave is the AXI Offset Address.
What's also important is to set a Timing constraint on the Differential PCI CLK.
Mapping the PCIe Data Signals isn't done over a constraint. You have to do it over Package Pins.
You can find Package Pins when you Open the Implemented Design and then go to Window->Package Pins.
In the Bottom of your window you can see the I/O Banks with the Pins and select the signals you want to map.
This Implementation hadn't implemented any DMA Transactions so when you write over your Driver to this Device it's not Buffered in the Main Memory of your System.
Actually I'm fast enough with that but it would also be nice to try a DMA Implementation.
Writing a Driver or Userspace Application isn't really hard. I will publish a sample code here in one of my next Posts where I try to explain a bit about it.
For the Floating Point Version I were just able to use generate and could implement n Independent Filter for every channel.
Cause the Fixed Point Filter is much faster I can Pipeline it through all channels and it's still fast enough.
That gives me this total resource consumption of my IP:
- Slice LUT's -> 2745 (4.33%)
- Slice Registers -> 5392 (4.25%)
- F7 Muxes -> 408 (1.29%)
- RAMB18 -> 0
- DSPs -> 16 (6.67%)
So with this resource usage I think there is still enough Space to implement a STFT on the Artix 7 ;-)
But I won't talk too much about the Filter Implementation.
I think it could be interesting to Show you the PCIe Block Diagram and what's important to get it ready.
MSI Request -> '0'
axi_aresetn -> '1'
Utility Buffer:
- Set to IBUFDSGTE
- PCIE:BARs -> Bar0 Size to AXI Device size
- PCIE:BARs -> AXI-PCIe BAR Translation Offset to AXI Offset
- AXI:BARS -> AXI to PCIe Translation Offset to AXI Offset
When you go to the Address Editor you have to map the AXI Slave to the Address Map.
Then you see there the Address Range, the Start Address of your Slave is the AXI Offset Address.
What's also important is to set a Timing constraint on the Differential PCI CLK.
Mapping the PCIe Data Signals isn't done over a constraint. You have to do it over Package Pins.
You can find Package Pins when you Open the Implemented Design and then go to Window->Package Pins.
In the Bottom of your window you can see the I/O Banks with the Pins and select the signals you want to map.
This Implementation hadn't implemented any DMA Transactions so when you write over your Driver to this Device it's not Buffered in the Main Memory of your System.
Actually I'm fast enough with that but it would also be nice to try a DMA Implementation.
Writing a Driver or Userspace Application isn't really hard. I will publish a sample code here in one of my next Posts where I try to explain a bit about it.
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