FPGA 50Hz Notch and 1-10Hz Highpass Filter Implementation

This Weekend I was working on implementing some Filters on the FPGA for my ADS Embedded Project.

First I tried it with Fixed Point Arithmetic as I mentioned it in my previous Post. But after reading and trying a bit with it I decided to Switch to Floating Point cause I still have a working Floating Point Adder from a University Project and some thinking about it let's me Implement a working Floating Point Multiplier and the Integer to Floating Point Conversion Units.

I don't think that I will release the Units here because I don't know about the licensing. But If you are interested in these Parts send me a mail and I will send you the Code you Need.

After I tested them and removing some bugs I started to Implement my Filter.
In my University I started to let Matlab create the Filters with the HDL Coder but it doesn't work pretty well and take much resources, because I don't optimized it well in the Settings.

But the Simulink Models I created for that were very helpful, because now I had a Block Diagram for my Filter and can implement the calculation with the Floating Point Parts in a State Machine.

First I were a bit sceptical because I don't know If they would be fast enough because a Floating Point Operation tooks about 25cycles and there were a few of them in my Models.
But after I realized the Highpass, I saw in my Timing diagram that it's fast enough to cascade it with the Notch and be able to use the same Floating Point Instances again and just extend the State Machine.
The longest Operation I saw in the Simulation were about 6.5µs, but my Input Data gets updated with a Maximum of 62,5µs (16kSPS)

The Resource usage of this Filter were pretty low:
  • Slice LUT's -> 870 (1.37%)
  • Slice Registers -> 942 (0.74%)
  • RAMB18 -> 1 (0.37%)
  • DSPs -> 2 (0.83%)
The Percentage refer to the XC7A100T which I'm using and it's the Post-Synthesis Usage.

So, enough about that. Now I will Show you Some Pictures of the Simulation and the Simulink Models.

The Highpass VHDL Implementation vs. Matlab Plot -> Step Response
 
 
With the Red Numbers I numerized the Multiplier and Adders
The Blue Numbers were numerizing the Sequence for the State Machine
 
1-10Hz Highpass Model -> DF2-SOS 
 
 

 
50 Hz Notch Model -> DF2-SOS

You can see that the Notch Model is a 3-fold cascaded  DF2-SOS at which I were a bit Concerned about, but as I mentioned earlier It WORKS :-)

Thinking a bit about the usage, I should be able to Multiplexing the Gains and implement with that the Gains for other Sample rates, which would make it more useful and It wouldn't take too much Resources.

Tomorrow I will Implement it in my actual IP Core and do some "Benchmark" Testing with an ECG of my own.

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