FPGA 50Hz Notch ... Second Version
Normally I wanted to Show you yesterday my results of the Filter Implementation, but I found no time so I will Show it today.
Cause my Electrodes hadn't good contact you won't see a real ECG but you can see how it filters.
Orange is the Original unfiltered Signal.
Blue is the Signal filtered with the FPGA.
Yellow the Signal filtered with Matlab.
Matlab and the FPGA uses the same Coefficients so there's much more Noise from the FPGA.
I thought I can reduce the Noise with double Floating Point Precision but that won't met my Timings.
That let me come back to Fixed Point Arithmetic. So I made this evening a Fixpoint Version I used 25 Bits Precomma and 39 Bits Pastcomma. So in Sum I'm using 64 Bit Vectors and 128 for Multiplication.
When I wrote it I used the STD_LOGIC_ARITH and STD_LOGIC_UNSIGNED librarys. When I simulated it first I hadn't get the right results so I thought about it and I realized that Unsigned is the wrong library I had to use Signed, cause I had subtraction and can get negative Inputs and Coefficients ...
After correcting this It runs fine, compared to my Floating Point Version it's much better!
Here a comparison:
Out1 is the Floating Point Version
dOut1 is the Fixed Point Version
You can see the Fixed Point Version is less noisy and so it could get closer to my Matlab Results.
The Timing of the Fixed Point Version is much faster it just Needs about fixed 590ns compared to 3.7µs - 29.68µs
And the Resource usage is also not too high:
The Simulink Models from the previous Post are the same. If anyone knows a good Syntax Highlighting Code for VHDL please let me know ;-)
Perhaps this code would help Someone.
It would also be Possible to make the fix Point Parameters generic and so more useful.
And to add the coefficients as Registers so you can Change them in System.
Cause my Electrodes hadn't good contact you won't see a real ECG but you can see how it filters.
Orange is the Original unfiltered Signal.
Blue is the Signal filtered with the FPGA.
Yellow the Signal filtered with Matlab.
Matlab and the FPGA uses the same Coefficients so there's much more Noise from the FPGA.
I thought I can reduce the Noise with double Floating Point Precision but that won't met my Timings.
That let me come back to Fixed Point Arithmetic. So I made this evening a Fixpoint Version I used 25 Bits Precomma and 39 Bits Pastcomma. So in Sum I'm using 64 Bit Vectors and 128 for Multiplication.
When I wrote it I used the STD_LOGIC_ARITH and STD_LOGIC_UNSIGNED librarys. When I simulated it first I hadn't get the right results so I thought about it and I realized that Unsigned is the wrong library I had to use Signed, cause I had subtraction and can get negative Inputs and Coefficients ...
After correcting this It runs fine, compared to my Floating Point Version it's much better!
Here a comparison:
dOut1 is the Fixed Point Version
You can see the Fixed Point Version is less noisy and so it could get closer to my Matlab Results.
The Timing of the Fixed Point Version is much faster it just Needs about fixed 590ns compared to 3.7µs - 29.68µs
And the Resource usage is also not too high:
- Slice LUT's -> 2510 (3.96%)
- Slice Registers -> 4976 (3.92%)
- F7 Muxes -> 64 (0.2%)
- RAMB18 -> 0
- DSPs -> 16 (6.67%)
The Simulink Models from the previous Post are the same. If anyone knows a good Syntax Highlighting Code for VHDL please let me know ;-)
Perhaps this code would help Someone.
It would also be Possible to make the fix Point Parameters generic and so more useful.
And to add the coefficients as Registers so you can Change them in System.
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