ADS1299 Embedded System Intro

So actually I'm working on an Embedded Linux System which will read and Process Data from an TI ADS1299 ECG/EEG Frontend Chip.

The Hardware of the System is a NXP i.MX6 Dual Core Processor with 2GB of RAM.
So I bought a System on Module from Solid-Run, because I have no Experience in designing a Embedded System and I think it would be too expensive to develop and produce it only for my own purposes.
So I only made the Baseboard for the SOM. It was also my first design with KiCAD, so I made some mistakes on it.
But it works pretty good and the things I need are ok.
To Access the ADS1299 I made also a custom board connected with a Hirose DF40 Connector. I Access the ADS over a Artix-7 with PCIe.
Using PCIe allows me to Access it easily over Memory Mapping so I don't have to do much with busses and drivers in Linux.

Actually I'm able to Access and read out all Channels of the ADS fast enough over PCIe.
What's pretty cool. But it wasn't as easy as I thought when I started the Project.

I will Show you some of my Problems and mistakes on the Boards as also in Linux in the next Posts.

My next Plans of this Project is to implement some Filters(Highpass + 50Hz Notch or Comb) in the FPGA. And look if I could do also a STFT on the FPGA.

The code for the FPGA is in VHDL which I had to learn in the University. But I hope that I will find some day time to learn Verilog, SystemC or SystemVerilog though I think the Syntax there is quite a bit easier.

I'm not sure if I will Release here the complete VHDL code. But I will Show you some Tools I had to write to get it all working.

And if you're also Planning an Embedded Project and need a fast Bus System for a short distance, try PCIe it's easier than most People Claim.

Kommentare

Kommentar veröffentlichen

Beliebte Posts aus diesem Blog

FPGA 50Hz Notch and 1-10Hz Highpass Filter Implementation

Bild
This Weekend I was working on implementing some Filters on the FPGA for my ADS Embedded Project. First I tried it with Fixed Point Arithmetic as I mentioned it in my previous Post. But after reading and trying a bit with it I decided to Switch to Floating Point cause I still have a working Floating Point Adder from a University Project and some thinking about it let's me Implement a working Floating Point Multiplier and the Integer to Floating Point Conversion Units. I don't think that I will release the Units here because I don't know about the licensing. But If you are interested in these Parts send me a mail and I will send you the Code you Need. After I tested them and removing some bugs I started to Implement my Filter. In my University I started to let Matlab create the Filters with the HDL Coder but it doesn't work pretty well and take much resources, because I don't optimized it well in the Settings. But the Simulink Models I created for that were v
Mehr anzeigen

FPGA Notch the third and PCIe Block Diagram

Bild
Today I implemented the Fixed Point Version of my Filter in my IP Core. For the Floating Point Version I were just able to use generate and could implement n Independent Filter for every channel. Cause the Fixed Point Filter is much faster I can Pipeline it through all channels and it's still fast enough. That gives me this total resource consumption of my IP: Slice LUT's -> 2745 (4.33%) Slice Registers -> 5392 (4.25%) F7 Muxes -> 408 (1.29%) RAMB18 -> 0 DSPs -> 16 (6.67%) The Time needed for Filtering 8 Channels is 9.56µs. So with this resource usage I think there is still enough Space to implement a STFT on the Artix 7 ;-) But I won't talk too much about the Filter Implementation. I think it could be interesting to Show you the PCIe Block Diagram and what's important to get it ready. MSI Request -> '0' axi_aresetn -> '1' Utility Buffer: Set to IBUFDSGTE AXI Memory Mapped to PCI Express PCIE:BARs ->
Mehr anzeigen

FPGA 50Hz Notch ... Second Version

Bild
Normally I wanted to Show you yesterday my results of the Filter Implementation, but I found no time so I will Show it today. Cause my Electrodes hadn't good contact you won't see a real ECG but you can see how it filters. Orange is the Original unfiltered Signal. Blue is the Signal filtered with the FPGA. Yellow the Signal filtered with Matlab. Matlab and the FPGA uses the same Coefficients so there's much more Noise from the FPGA. I thought I can reduce the Noise with double Floating Point Precision but that won't met my Timings. That let me come back to Fixed Point Arithmetic. So I made this evening a Fixpoint Version I used 25 Bits Precomma and 39 Bits Pastcomma. So in Sum I'm using 64 Bit Vectors and 128 for Multiplication. When I wrote it I used the STD_LOGIC_ARITH and STD_LOGIC_UNSIGNED librarys. When I simulated it first I hadn't get the right results so I thought about it and I realized that Unsigned is the wrong library I had to use
Mehr anzeigen