Posts

Iterative Radix2-FFT on FPGA

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Hey, so now I'm ready with my first FFT Implementation. Like I mentioned in my earlier Post I want to implement a Iterative Radix2 FFT Algorithm. You can see a Pseudocode on Wikipedia: https://en.wikipedia.org/wiki/Cooley%E2%80%93Tukey_FFT_algorithm#Data_reordering,_bit_reversal,_and_in-place_algorithms I compared it with a C++ Implementation of it and it's relative exact. With relative I mean that there are rounding Errors in it or Overflow Errors I don't exactly know. The Picture of the Simulation Shows just the Imaginary Part. The Real Part is nearly 0 that means it's about -1 and 1. Calculation Times@100Mhz Input Clock are about 56µs@128Samples and 23µs@64Samples . So it's not a pretty fast Implementation and it's not really resource efficient I think. It would be also possible to work with lower Resolution actually I'm using 64bit Fixed Point Numbers (EN25_39). Resource Usage at 128Samples is: Slice LUT's -> 18988 (29.95%

Actual State of ADS Project

So I had a little break because I'm in the middle of our Exam Phase. But I want to give you an Update about my Progress of the ADS Embedded Project ( I think I Need a nicer and shorter Project Name). DF2SOS Filter: The Filter itself is now working perfect there is no more noise as we have seen on the Floating Point Version. So Matlab and the FPGA Version were working identically. :-) I thought about making it more General. Actually the Coefficients were hard synthesized and could only get changed when you synthesize it new which is very time Consuming... So when I have enough Resources I would like to cut the code at the states of one DF2SOS "Module" and let it Loop through it. And the constants I will fetch from the Block RAM. The constants and number of Loops through the DF2SOS I will write over an extra PCIe Bar to my Device. I think that's quite a nice Approach to make it more General cause you just give the Constants to your User Program and you could

FPGA Notch the third and PCIe Block Diagram

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Today I implemented the Fixed Point Version of my Filter in my IP Core. For the Floating Point Version I were just able to use generate and could implement n Independent Filter for every channel. Cause the Fixed Point Filter is much faster I can Pipeline it through all channels and it's still fast enough. That gives me this total resource consumption of my IP: Slice LUT's -> 2745 (4.33%) Slice Registers -> 5392 (4.25%) F7 Muxes -> 408 (1.29%) RAMB18 -> 0 DSPs -> 16 (6.67%) The Time needed for Filtering 8 Channels is 9.56µs. So with this resource usage I think there is still enough Space to implement a STFT on the Artix 7 ;-) But I won't talk too much about the Filter Implementation. I think it could be interesting to Show you the PCIe Block Diagram and what's important to get it ready. MSI Request -> '0' axi_aresetn -> '1' Utility Buffer: Set to IBUFDSGTE AXI Memory Mapped to PCI Express PCIE:BARs ->

FPGA 50Hz Notch ... Second Version

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Normally I wanted to Show you yesterday my results of the Filter Implementation, but I found no time so I will Show it today. Cause my Electrodes hadn't good contact you won't see a real ECG but you can see how it filters. Orange is the Original unfiltered Signal. Blue is the Signal filtered with the FPGA. Yellow the Signal filtered with Matlab. Matlab and the FPGA uses the same Coefficients so there's much more Noise from the FPGA. I thought I can reduce the Noise with double Floating Point Precision but that won't met my Timings. That let me come back to Fixed Point Arithmetic. So I made this evening a Fixpoint Version I used 25 Bits Precomma and 39 Bits Pastcomma. So in Sum I'm using 64 Bit Vectors and 128 for Multiplication. When I wrote it I used the STD_LOGIC_ARITH and STD_LOGIC_UNSIGNED librarys. When I simulated it first I hadn't get the right results so I thought about it and I realized that Unsigned is the wrong library I had to use

FPGA 50Hz Notch and 1-10Hz Highpass Filter Implementation

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This Weekend I was working on implementing some Filters on the FPGA for my ADS Embedded Project. First I tried it with Fixed Point Arithmetic as I mentioned it in my previous Post. But after reading and trying a bit with it I decided to Switch to Floating Point cause I still have a working Floating Point Adder from a University Project and some thinking about it let's me Implement a working Floating Point Multiplier and the Integer to Floating Point Conversion Units. I don't think that I will release the Units here because I don't know about the licensing. But If you are interested in these Parts send me a mail and I will send you the Code you Need. After I tested them and removing some bugs I started to Implement my Filter. In my University I started to let Matlab create the Filters with the HDL Coder but it doesn't work pretty well and take much resources, because I don't optimized it well in the Settings. But the Simulink Models I created for that were v

Fix Point Solver

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In my last Post I wrote about my Embedded ADS Project and that I want to implement some Filters. For my Filter implementation I let Matlab calculate the coefficients and then build and simulate it in Simulink. Now I want to describe the Filter in VHDL though I Need there any Kind of Point Arithmetics I decided to test it with Fixed Point. To get the right sizes I Need and to easy translate binary Fixpoint Numbers to Real values I wrote a little helpful tool for that. I hadn't found a really good tool so I decided to publish my tool here so any one could use or Improve it. If you found a big bug or you had done some improvement by your own so please write me and I can update it here. Now a Picture of my Tool:  With the Radio Buttons you can Switch between the Conversion Modes. It's possible that the Program will get killed if you won't write a number or rather no numericals in the Input Boxes. So please don't look too long at the Code it's just qu

ADS1299 Embedded System Intro

So actually I'm working on an Embedded Linux System which will read and Process Data from an TI ADS1299 ECG/EEG Frontend Chip. The Hardware of the System is a NXP i.MX6 Dual Core Processor with 2GB of RAM. So I bought a System on Module from Solid-Run, because I have no Experience in designing a Embedded System and I think it would be too expensive to develop and produce it only for my own purposes. So I only made the Baseboard for the SOM. It was also my first design with KiCAD, so I made some mistakes on it. But it works pretty good and the things I need are ok. To Access the ADS1299 I made also a custom board connected with a Hirose DF40 Connector. I Access the ADS over a Artix-7 with PCIe. Using PCIe allows me to Access it easily over Memory Mapping so I don't have to do much with busses and drivers in Linux. Actually I'm able to Access and read out all Channels of the ADS fast enough over PCIe. What's pretty cool. But it wasn't as easy as I thought wh